1. Field of the Invention
The present invention relates to a semiconductor device and a control method thereof, and more particularly relates to a semiconductor device including a DLL circuit and a control method of the semiconductor device.
2. Description of Related Art
In a semiconductor device that operates in synchronism with a clock signal such as a synchronous DRAM (Dynamic Random Access Memory), an internal clock signal that is phase-controlled is required in some cases. In general, such an internal clock signal is generated by a DLL (Delay Locked Loop) circuit (see Japanese Patent Application Laid-open No. 2005-192164). The DLL circuit includes a delay line that delays an internal clock signal and its amount of delay is controlled by a count value of a counter circuit.
In a general DLL circuit, the count value is counted up or counted down so that a rising edge of a replica clock signal serving as a target of control matches a rising edge of an input clock signal serving as a reference. Accordingly, when the rising edge of the replica clock signal appears during the low level of the input clock signal to represent that the phase of the replica clock signal advances with respect to the phase of the input clock signal, the amount of delay of the delay line is increased. On the other hand, when the rising edge of the replica clock signal appears during the high level of the input clock signal to represent that the phase of the replica clock signal delays with respect to the phase of the input clock signal, the amount of delay of the delay line is decreased.
However, the general DLL circuit explained above is required to have an adjustable range in which a counter circuit can be controlled being more than a 1 clock cycle. The circuit size of the delay line is thus increased.